I do a lot of cross compilations. With different software elements. But sometimes I want to kick their authors into ass…
There is a good sign when you see $(CC) in Makefiles as it shows that author of code learnt that “gcc” is not the only compiler. But this is not the only compiler you should know about.
Recently I was adding one component (will save a name) into OpenEmbedded as this is one of dependencies for some bigger project (which I do not want to blog about). Argh… I managed to cross built it but patches are UGLY (will get better).
Using $(CC) to build everything is just broken. Especially when you need to compile a tool which will generate some code to get everything built. There is $(BUILD_CC) for it but you have to use it wisely. If there are common parts then compile them with $(BUILD_CC) if you need to run it and with $(CC) if you not. This way we, cross compilation guys, can just do “./configure;make;make install;package” is it native or cross build. Autotools (die, die, die) are able to handle that — so is your code if you write Makefiles properly.
But do not reuse same object files for target and native binaries — let it be “common.o” and “native/common.o” for example. OK, if you do only native builds then it will take a bit more disk space but we have 2012 not 1995… Storage is cheap.
There is also $(HOST_CC) but that’s for other post…
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There are other compilers than $(CC) was originally posted on Marcin Juszkiewicz website
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